1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a layout of a semiconductor memory device.
2. Description of the Background Art
FIG. 8 shows a layout of an entire chip of a conventional 4M bit dynamic random access memory (referred to as DRAM hereinafter).
Referring to FIG. 8, two 2M bit memory array blocks 2A and 2B are formed on a semiconductor substrate 1. Each of memory array blocks 2A and 2B comprises eight 256K-bit subarrays 3. A column decoder 4 is allocated between memory array blocks 2A and 2B. A row decoder 5A and a row decoder 5B are allocated at the sides of memory array blocks 2A and 2B, respectively. Power supply lines Vcc and Vss are arranged at the peripheral edge of semiconductor substrate 1.
FIG. 9 shows a detailed structure of region A of FIG. 8. Subarray 3 comprises a plurality of bit lines BL and BL, a plurality of word lines WL crossing the plurality of bit lines, and a plurality of memory cells MC provided at crossings of the plurality of bit lines BL and BL and the plurality of word lines WL. The plurality of bit lines form a plurality of bit line pairs BL and BL.
A plurality of sense amplifiers 6 are provided corresponding to the plurality of bit line pairs BL and BL. Each sense amplifier 6 is connected to a corresponding bit line pair BL and BL. The plurality of sense amplifiers 6 are arranged in a direction perpendicular to bit lines BL and BL to form a sense amplifier train (sense amplifier group).
The plurality of sense amplifiers 6 are connected to sense amplifier drive lines SP and SN. Sense amplifier drive line SP is connected to power supply line Vcc extending parallel to bit lines BL and BL via a drive transistor 7 formed of a P channel MOS transistor. Sense amplifier drive line SN is connected to power supply line Vss extending parallel to bit lines BL and BL via a drive transistor 8 formed of an N channel MOS transistor.
The gate of drive transistor 7 is connected to signal line SO for receiving a sense amplifier activation signal. The gate of drive transistor 8 is connected to signal line SO for receiving a sense amplifier activation signal.
FIG. 10 shows a detailed structure of the sense amplifier. Sense amplifier 6 comprises N channel MOS transistors 61 and 62, and P channel MOS transistors 63 and 64.
The drain of transistor 61 is connected to bit line BL and the drain of transistor 62 is connected to bit line BL. Both the sources of transistors 61 and 62 are connected to node n1. The gate of transistor 61 is connected to bit line BL, and the gate of transistor 62 is connected to bit line BL. The drain of transistor 63 is connected to bit line BL, and the drain of transistor 64 is connected to bit line BL. Both the sources of transistors 63 and 64 are connected to node n2. The gate of transistor 63 is connected to bit line BL, and the gate of transistor 64 is connected to bit line BL. Node n1 is connected to sense amplifier drive line SN, and node n2 is connected to sense amplifier drive line SP.
The fall of potential of sense amplifier drive line SN to a low level (logical low) causes the lower potential of bit lines BL and BL to attain a low level. A rise of potential of sense amplifier drive line SP to a high level (logical high) causes the higher potential of bit lines BL and BL to attain a high level. Thus, the potential difference between bit lines BL and BL is amplified.
The operation of the DRAM shown in FIGS. 8 and 9 will be explained hereinafter.
Row decoders 5A and 5B select any of the plurality of word lines WL to pull the potential of that word line WL to a high level. This turns on the transfer gates in the plurality of memory cells MC connected to the selected word line WL, whereby data is read out to the corresponding bit line BL or BL from the memory cells MC. As a result, charge flows to the bit lines BL or BL to change the potential thereof. Thus, potential difference is generated between bit lines BL and BL of each pair.
When the sense amplifier activation signal applied to signal line SO attains a high level, drive transistor 8 is turned on. This causes the power supply potential of low level on power supply line Vss to be provided to sense amplifier drive line SN. As a result, each sense amplifier 6 pulls down the lower potential of bit lines BL and BL to a low level.
When the sense amplifier activation signal applied to signal line SO attains a low level, drive transistor 7 is turned on. This causes the power supply potential of high level on power supply line Vcc to be provided to sense amplifier drive line SP. As a result, each sense amplifier 6 pulls up the higher potential of bit lines BL and BL to a high level. Thus, the sense operation of each sense amplifier 6 is carried out.
Increase in integration density and capacity of a DRAM results in the increase of sense amplifiers 6 connected to each sense amplifier drive lines SP and SN and increase in the length of each sense amplifier drive lines SP and SN.
Accordingly, the sensing time of a sense amplifier 6 located remote from drive transistors 7 and 8 becomes longer. A location remote from drive transistors 7 and 8 has a disadvantage that the pull up/down of the potential of sense amplifier drive lines SP and SN is not sufficient. This means that a sense amplifier 6 located remote from drive transistors 7 and 8 cannot sufficiently amplify the potential difference on bit lines BL and BL. 10 This may result in an erroneous operation.